Embodiments of the present invention relate generally to memory devices. Memory devices are used in many different types of systems to store code and data. Code and data are sometimes stored in two separate memories due to their access requirements. For example, code is typically written to a memory device as a large block of data during system manufacturing or code installation or update. Code is read in random fashion, directed by program counters, jumps and branches in software routines. Most data is written or read in blocks during application processing.
Direct execution of instructions stored in a memory requires that those instructions be made available in their correct form within relatively short initial access latency, perhaps 100 nS. Within the capabilities of the logic on these memories, it is not feasible to do more than single cell correction of the instructions prior to exporting these instructions to the system.
In many cases, multi-cell errors appear first as a single-cell error. At some later time, a second error occurs within the same codeword. With conventional techniques, this multi-cell error is not correctable and faulty data is returned to the system.
The use of the same reference symbols in different drawings indicates similar or identical items.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn,to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.